1. Field of the Invention
This invention relates to a memory of a sequential access type and more particularly to such a sequential-access memory which is automatically refreshed and has an increased memory capacity.
2. Related Art
There have been proposed various kinds of sequential-access memories of dynamic types which are, in general, suitable for storing musical data such as tone pitch data and tone color data for electronic musical instruments.
One of the inventors of the present application has proposed a sequential-access memory of such kind in Japanese Patent Application No. 58-214898 which was laid-open under No. 60-107795. FIG. 1 shows the structure of the sequential-access memory 10 which is arrange to store "n" pieces of bits. (Four memories 10 connected in parallel are shown in FIG. 1.) In FIG. 1, shown at 11.sub.1 to 11.sub.n are a row of conventional three-transistor type dynamic RAM storage cells each of which comprises three transistors T3 to T5 and a capacitor C. The transistor T4 cooperates with the capacitor C to form an information storage element. More specifically, the transistor T4 conducts when the capacitor C is charged, and is off when the capacitor C is discharged. When a gate of the transistor T5 of the cell 11.sub.i ("i" is any one of "1" to "n"), that is, a read selection line R.sub.i of the cell 11.sub.i, is supplied with a selection signal S.sub.i of "1", the transistor T5 of the cell 11.sub.i conducts to connect the transistor T4 of the cell 11.sub.i to a read data line 12. The read selection line R.sub.i of the cell 11.sub.i is connected to a gate of the transistor T3 of the preceding stage cell 11.sub.i-1, that is, a write selection line W.sub.i-1 of the preceding stage cell 11.sub.i-1. When a gate of the transistor T3 of the cell 11.sub.i, that is, a write selection line W.sub.i of the cell .sub.i, is supplied with a selection signal S.sub.i+1 of "1", the transistor T3 of the cell 11.sub.i conducts to connect a data write line 13 to the capacitor C of the cell 11.sub.i, whereby the capacitor C is charged or discharged in accordance with a signal on the data write line 13. The write selection line W.sub.i of the cell 11.sub.i is connected to the read selection line R.sub.i+1 of the succeeding stage cell 11.sub.i+1.
Thus, the dynamic storage cells 11.sub.1 to 11.sub.n are serially connected in such a manner that the read selection line R.sub.i of the cell 11.sub.i is connected to the write selection line W.sub.i-1 of the preceding stage cell 11.sub.i-1. All the cells 11.sub.1 to 11.sub.n are connected to the common read data line 12 and to the common write data line 13. The memory 10 is driven by a pair of clock signals .phi.1 and .phi.2 180.degree. out of phase from each other (see FIGS. 2-(a) and 2-(b)), each clock having a period of T. The selection signals S.sub.1 to S.sub.n are rendered "1" one after another in synchronism with the clock signal .phi.2 to achieve a sequential access to the cells 11.sub.1 to 11.sub.n, as shown in FIG. 2.
In operation, when the selection signal S.sub.1 (FIG. 2-(d)) is rendered "1" to access the storage cell 11.sub.1, the data contained in the cell 11.sub.1 is outputted onto the read data line 12 as read data DR.sub.1 and stored into a latch 14 by the clock signal .phi.2 (FIG. 2-(b)). The data DR.sub.1 thus read from the cell 11.sub.1 and stored in the latch 14 is inverted by an inverter 15 and outputted from this memory 10 as an output data OUT1 (FIG. 2-(h)). If a write pulse signal W (FIG. 2-(k)) is at the "0" level at this time, the output data OUT1 is also fed through a selector 16 to a delay circuit 17 and stored thereinto by the clock signal .phi.1 (FIG. 2-(a)). The data OUT1 (or the data DR.sub.1) thus stored into the delay circuit 17 is outputted therefrom onto the write data line 13 by the next clock .phi.2. The next selection signal S.sub.2 is rendered "1" simultaneously with this clock signal .phi.2, so that the data outputted onto the write data line 13, which is the same data as the data DR.sub.1 read from the cell 11.sub.1, is written into the same cell 11.sub.1, thereby the cell 11.sub.1 being refreshed. If the write pulse signal W is at the "1" level, write data DW.sub.1 (FIG. 2-(j)) from the exterior passes through the selector 16 and is stored into the delay circuit 17, so that the new data DW.sub.1 is written into the cell 11.sub.1. The data on the write data line 13 is also outputted from this memory 10 as data OUT2 (FIG. 2-(i)). The operation is true of the cells 11.sub.2 to 11.sub.n. The read data line 12 is pre-charged immediately before each reading operation through a transistor 18 which is conducted by a pre-charge control pulse signal PC (FIG. 2-(c)) generated in synchronization with the clock signal .phi.1.
With the above arrangement, all the memory cells 11.sub.1 to 11.sub.n of the memory 10 are sequentially accessed and are therefore automatically refreshed. In addition, the memory 10 has a function to delay each data by a time period corresponding to "n" cycles of the clock signal .phi.1, .phi.2. However, the memory 10 is not satisfactory in the following respects:
When the number "n" of storage cells is augmented to increase the storage capacity, the access time for each cell is also increased, so that the refreshing rate is decreased, which may result in an insufficient refreshing of each storage cell.
Moreover, in order to test the memory 10, it is necessary to apply the selection signals S.sub.1 to S.sub.n to the memory 10 one by one and to compare the inputted data with the outputted data for each selection signal.